Honored Contributor
Honored Contributor@changjianchun,
here is an update of what you probably intended your VHDL description to do. The counter cnt has been extended to 32 bits and 4 more HEX displays are added. In case your board has only 4, you should use the 16 most significant bits of the cnt counter to display, as you will otherwise not see anything.library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity display is
port (
c: in std_logic_vector (3 downto 0);
HEX: out std_logic_vector (6 downto 0)
);
end entity display;
architecture logic of display is
begin
process (c)
begin
case c is
when X"0" =>
HEX <= "1000000";
when X"1" =>
HEX <= "1111001";
when X"2" =>
HEX <= "0100100";
when X"3" =>
HEX <= "0110000";
when X"4" =>
HEX <= "0011001";
when X"5" =>
HEX <= "0010010";
when X"6" =>
HEX <= "0000010";
when X"7" =>
HEX <= "1111000";
when X"8" =>
HEX <= "0000000";
when X"9" =>
HEX <= "0010000";
when X"a" =>
HEX <= "0001000";
when X"b" =>
HEX <= "0000011";
when X"c" =>
HEX <= "1000110";
when X"d" =>
HEX <= "0100001";
when X"e" =>
HEX <= "0000110";
when X"f" =>
HEX <= "0001110";
end case;
end process;
end architecture;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter_test is
port (
CLOCK_50: in std_logic;
KEY: in std_logic_vector (3 downto 0);
HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7: out std_logic_vector (6 downto 0)
);
end entity counter_test;
architecture behav of counter_test is
component display is
port (c: in std_logic_vector (3 downto 0);
HEX: out std_logic_vector (6 downto 0));
end component;
signal cnt: std_logic_vector (31 downto 0);
signal c0,c1,c2,c3,c4,c5,c6,c7 : std_logic_vector (3 downto 0);
signal a,b,c,d,e,f,n,m:std_logic_vector (6 downto 0);
signal reset_n : std_logic;
signal CLOCK : std_logic;
begin
reset_n <= KEY(0);
clock <= CLOCK_50;
d0: display port map(c0,a);
d1: display port map(c1,b);
d2: display port map(c2,n);
d3: display port map(c3,m);
d4: display port map(c4,c);
d5: display port map(c5,d);
d6: display port map(c6,e);
d7: display port map(c7,f);
c0 <= cnt (3 downto 0);
c1 <= cnt (7 downto 4);
c2 <= cnt (11 downto 8);
c3 <= cnt (15 downto 12);
c4 <= cnt (19 downto 16);
c5 <= cnt (23 downto 20);
c6 <= cnt (27 downto 24);
c7 <= cnt (31 downto 28);
HEX0<= a;
HEX1<= b;
HEX2<= n;
HEX3<= m;
HEX4<= c;
HEX5<= d;
HEX6<= e;
HEX7<= f;
process
begin
wait until (CLOCK'event and CLOCK = '1');
if (reset_n = '0') then
cnt <= X"00000000";
else
cnt <= cnt + 1;
end if;
end process;
end architecture behav;