New ContributorQuartus/Chip Planner: How can I lock in design and simply change clock speed?
I have the following problem meeting timing on a Max10 (M02):
I have a design resolving to 90% utilization. Uses a PLL (dual clocks in system)
When the "fast" clock is set to 234 mhz I get a fast clock FMax of 243 mhz and everything meets timing. If I increase the PLL to 243.. or any number between 230-243 I get a drop in FMAX to below 225 and the design does not meet timing. Everything else remains unchanged. (Same is true for any other random immaterial change in the code.. I get a random FMAX changes in the 20-30mhz range)
This feels like a design utilization / chip layout issue.
I hate to leave 10 mhz on the table.. since the design can technically run at 243. Is there a way to lock in the design/layout at 234 mhz (using chip planner).. and then simply change the PLL speed to 243mhz?
I'm a beginner to intermediate user on Altera tools.. so I don't know anything...
PS - design compiles using best area / best performance settings.
Fmax is not gospel. It's an estimate of what the potential maximum frequency of the currently placed and routed design *should* be able to run at. There's no guarantee that it will. That Fmax may be just at the cusp of 0 ns of slack somewhere. You use Fmax to say, OK, in the future, I can try adjusting my design to run at this speed and the Fitter should be able to provide me a design that works at that speed (though no guarantees if you're pushing it).
If you increase the speed of your design by changing the PLL settings and your .sdc file, the Fitter will run in a different way to make sure the design meets timing at that speed (if it can), then reporting on an Fmax that *may* be faster than what you are running at. In other words, the Fitter gives you what you ask for.
As for locking down the design, the Standard edition of Quartus does include the incremental compilation feature, which lets you lock down and reuse the post-fit netlists of parts of your design you designate (called design partitions). This is useful for timing closure in a large design because you can close timing in just a part of the design and then lock it down (and continue locking down partitions as you get them to close timing) so it doesn't change the next time you compile. However, I don't think this is really what you are looking for.
In other device families, you can change PLL settings during runtime (dynamic PLL), but that's not available in MAX 10 devices.
