Forum Discussion
New ContributorQuartus/Chip Planner: How can I lock in design and simply change clock speed?
Fmax is not gospel. It's an estimate of what the potential maximum frequency of the currently placed and routed design *should* be able to run at. There's no guarantee that it will. That Fmax may be just at the cusp of 0 ns of slack somewhere. You use Fmax to say, OK, in the future, I can try adjusting my design to run at this speed and the Fitter should be able to provide me a design that works at that speed (though no guarantees if you're pushing it).
If you increase the speed of your design by changing the PLL settings and your .sdc file, the Fitter will run in a different way to make sure the design meets timing at that speed (if it can), then reporting on an Fmax that *may* be faster than what you are running at. In other words, the Fitter gives you what you ask for.
As for locking down the design, the Standard edition of Quartus does include the incremental compilation feature, which lets you lock down and reuse the post-fit netlists of parts of your design you designate (called design partitions). This is useful for timing closure in a large design because you can close timing in just a part of the design and then lock it down (and continue locking down partitions as you get them to close timing) so it doesn't change the next time you compile. However, I don't think this is really what you are looking for.
In other device families, you can change PLL settings during runtime (dynamic PLL), but that's not available in MAX 10 devices.
Regular ContributorHi,
As you increase the target Fmax, timing requirements is harder to meet and the optimal place & route to meet timing will be different.
That being said, locking down the design at 234MHz before changing the PLL target Fmax won't help.
Can you share the Report Timing from Timing Analyzer?
Which Quartus version are you using?
Regards,
Nurina
tschesnokThanks for your reply. I'm using 20.1.0 lite. (I would give you more detail.. but Quartus (like many other times) will not let me cut and paste it)
I'm confused. If my design is fully constrained.. with a clock defined at say 100 mhz.. and it results in meeting timing with an FMAX of 120 mhz.. are you telling me that I CAN'T run that design at 120mhz? What is the point of FMAX?
I'm suggesting the fitter is stupid.. it creates a high performance solution (but at the wrong PLL settings). When I change the PLL to match the fitting performance.. the fitting changes and gets worse.
Put another way.. (and this also happens) Let's say the design does NOT meet timing at 220 mhz.. but suggests (via FMAX) that it will meet timing at 200 mhz.. if I relax the clock to 200Mhz.. guess what.. my new FMAX is suddenly 180 mhz and it still fails...
Bottom line.. fitter sucks and it needs manual help. If I can't lock down the design with the free version of quartus.. well.. I'm out of luck since I'm not paying. I have not seen these erratic placer issues with Xilinx.
