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Modelsim stopped the simulation with an error, because a file called "../../rtl_work.filename" could not be found.
The file isn`t in the directory, so how to create this file?
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I'm not sure what that file is or how you would create it. If you post your project, someone may take a look.
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And let me ask you, what exactly do you mean with "modify it to add clk/reset generation".
Is it to add a clock and a reset from the IP catalog?
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Open the counter.vt file and search for 'clk' and 'reset_n' and you will see where I added my clk/reset generation. You need to do the same/similar in your own test bench file.
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For your information, actually i receive the clock from an external signal, so i just got an input port. In the waveform editor, you could generate a clock. Is it possible to work like that in Modelsim to or is it necessary to use the IP blocks as mentioned in my question above?
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The tutorial PDF tells you how to do it in Modelsim. My project and my suggestion is to do it in (Verilog) HDL in your test bench file. It's pretty simple, and yes almost all projects get set up like this.
Honored Contributor
