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Altera_Forum
Honored Contributor
11 years agoAttached is a simple counter + PLL project. The file 'counter.v' was written by hand, while 'simulation/modelsim/counter.vt' was generated by Procession->Start->Start Test Bench Template Writer.
I then added the test bench clk, reset generation to the template. Open the project, compile it, and then launch the RTL simulation. Modelsim should run for 100ns and the wave window should have all of the testbench (top level) signals. This is just an illustration of getting the basics working. Back in your project you are working on, you probably just need to run the "Start Test Bench Template Writer", modify it to add clk/reset generation, and then define the test bench in the Settings dialog box. If you are still stuck, post a .qar of your project ( or a dummy/simplified project if you can't share your full project ).