Quartus18.x issue3: if elsif errant

No, I exported on another design and doesn't work.

Strange behavior, I routed out RXD from Ethernet input LVDS. On LA is just '0'.

On TX appear just ARP replay, This is ok so no idea why it doesn't work.

Rtl simulator doesn't work too.

I am planning trash out everything from Altera, now Intel.

Design work as is on competitor platform, too many error come from tool never addressed.

I try'd constraint as suggested, no difference on constrained or not design.

Issue appear on something is stable for a long time, doesn't change at all where issue is present.

First issue reported:

Signal driving this logic come from received packet on Tx component. From where it is received to when is used some time in the order of uS elapses, signal doesn't change till next received packet, so during alll TX is like a constant.

Second issue:

Signal use a register was set in the previous reception of ARP/ICMP/UDP packet. One byte @10MHz has a period of 800nS, at almost 10 bytes of preamble are 8uS. This way I think is crazy suspect timing closure.

I found too many issue to simulator, programmer, Platform designer...

Found one subtle error on design was not related to this issue.

I cannot waste time to do beta test for free, write a report cost time, I have no time now and delivery date is very close.

Altera now Intel on my view is dead.

Best regards

Roberto