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Altera_Forum
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18 years ago

Quartus Web Edition 7.1 Schematic Symbol Error

Hi, I created a module in Verilog that I am including in a schematic as a symbol. The module has bus inputs called: input wire [23:0] ch1, input wire [23:0] ch10, input wire [23:0] ch...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Thank you, very good point, I think it is a bug, though.

I wrote a wrapper to my module with the first three characters being different for ch1 and ch11. The Quartus schematic tool is so far the only tool that has had a problem with using ch1[23:0] and ch11[23:0]. ModelSim is OK, even Quartus Verilog Synthesis is OK.

RAUL