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Altera_Forum's avatar
Altera_Forum
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18 years ago

Quartus Web Edition 7.1 Schematic Symbol Error

Hi, I created a module in Verilog that I am including in a schematic as a symbol. The module has bus inputs called: input wire [23:0] ch1, input wire [23:0] ch10, input wire [23:0] ch...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Nope,

You must think like a computer.

It is doing exactly as you ask.

I will space thinkgs out a little to help you see it better.

ch1 19 looks just like ch11 9

If you rename your inputs to something like;

ch1bit

ch2bit

...

ch11bit

etc

you will get what you want.

It is always a risk to name a signal with a number if you are going to vectorize it.

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