Quartus v18.0.1 Avalon Verification IP Suite Update?

The Avalon BFMs have not changed. That's why the document hasn't been updated. The clock and reset BFMs are source BFMs. They generate clock and reset to drive the clock and reset sink (inputs) to your component or system under test.

I guess I am not following properly. See attached screenshot. This is from Intel's reference design for the Verification IP Suite. The top IP that contains the clk/rst is what's missing from the current IP list. I thought this was the Clock Source BFM and Reset Source BFM but updated and split into two separate IP.

Thinking about it now, I'm assuming I can just replace this with a Clock Bridge and Reset Bridge to replicate it? And my other question would be what is the purpose of the clock and reset BFMs then when it is not being driven by the test bench? This is very new to me so I am trying to piece this together and understand it.

Yes, the clock source component is for synthesis. The BFMs are for simulation.

There is no other use for the BFMs. You use them to create a special testbench system specifically for simulation. To save time, you can generate this testbench system automatically from the Generate menu (Generate Testbench I think). If you choose the simple option, it replaces clocks and resets with clock and reset BFMs for control in your testbench program. If you choose the other option (forget what it's called right now), it will generate a testbench system with the appropriate BFMs attached to any exported interfaces in your system. See this online training for details:

https://www.intel.com/content/www/us/en/programmable/support/training/course/oaqsyssim.html

I'm following now. I was also not thinking clearly about how it works in relation to testbenches and realized I forgot some details. I will definitely check out the training course. Thank you so much!