Forum Discussion
Altera_Forum
Honored Contributor
11 years agoThe - isn't supported in Verilog and I believe it's not supported in VHDL. This may have been made just to keep them together. (For example, if you simulate the design, which requires writing out a .vo or .vho, it won't be compliant with the standard.)
That doesn't help, but just a guess as to why...