Quartus Timing Analyzer and Constraints...

I realize this is a lot to ask however, I'm not understanding completely how to constrain this project. Attached is a simplified version of my project. It uses an address bus, data bus, read and write lines, and a chipselect. One thing that I'm not understanding is what clock to use when constraining the input or output delay (Min and Max). This is because the clock on the flip-flops for my register in my "regTest" verilog module is a combination of RD or WR, address, and chipselect. (you can see this in the RTL netlist) I also have a dipswitch module that I read the value of dipswitches that needs to be constrained. All this is an area of confusion for me.

The other question I have is how to properly constrain the generated clock "OutClk" to its pin. Please ignore the crudity of this module, its a simplified version of the real thing.

I have attached the simplified version of my project along with a simple timing diagram of the signals coming from my NXP processor. The project works most of the time however, sometimes after a small change I have problems with either reading or writing. I believe this is because the project is not properly constrained. I'm wondering if someone would be so kind as to provide an example SDC file that shows proper constraints of this project?

Thanks in advance for your hard work, I really appreciate all the helps.

Brandon