Quartus system verilog interface parameter bug

Does anyone know of a workaround for the following System Verilog interface parameter bug?

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The short version:

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In some (not all) contexts, the default value of an interface parameter is used instead of the overriding value.

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The very long version (offending code is attached):

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Error message produced by following code:

Error (10232): Verilog HDL error at if_test.sv(44): index 4 cannot fall outside the declared range [3:0] for vector "io.in"

Observations of above message:

- The declared range of io.in is [7:0] not [3:0]

- The default paramater value of the interface would give a range for io.in of [3:0] as reported by the error message.