New Contributor
Super ContributorTwo things.
1) For a synthesized design, you shouldn't use an initial statement. It is not synthesizable. If you want to initialize the registers to all 0, rely on all the registers naturally initializing low or use a normal clocked process based on a reset signal.
2) The registers were implemented as memory because you created them as a 2D array and you are using synchronous writes. If you don't want to use a memory block, either use a Quartus assignment in the Assignment Editor to not implement gpr as a memory (I'm forgetting the assignment name right now but you can choose to implement as registers instead of memory) or don't use a 2D array to create the registers.
#iwork4intel
New ContributorThanks for the tips!
However, I am still confused about a certain aspects of this.
The code I showed you above stayed the same and was implemented in two different processors.
One was a pipelined processor and in that the register file was synthesised into altsync_ram and used memory bits.
The other processor was non-pipelined and the register file was synthesised into registers/ALMs and used no memory bits.
Im confused about how the same code can get synthesised differently just by being implemented in different top level designs.
Thanks
