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Altera_Forum's avatar
Altera_Forum
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7 years ago

Quartus show only dumber's incomplete view

Hi, It feels like being treated as a dumb by Quartus. For example, we have a very simple add one counter, `timescale 1ns / 1ns module test_grammar (count, clk, reset); output [1:0] ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

You code does not describe a register, hence why there are no registers in the RTL views, just inferred latches. You have it as if using both reset and clock as clocks. You need to change the code to: 


module test_grammar (count, clk, reset);
output  count;
input clk, reset;
reg  count;
initial
begin
count=0;
end
always @ (negedge clk or posedge reset) begin
  if reset begin
    count <= 0;
  end
  else begin
    count<=count+1;
  end
end
endmodule