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Altera_Forum's avatar
Altera_Forum
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7 years ago

Quartus show only dumber's incomplete view

Hi,

It feels like being treated as a dumb by Quartus. For example, we have a very simple add one counter,

`timescale 1ns / 1ns

module test_grammar (count, clk, reset);

output [1:0] count;

input clk, reset;

reg [1:0] count;

initial

begin

count=0;

end

always @ (negedge clk or posedge reset)

count<=count+1;

endmodule

And the clk and reset edges drives the FLIP-FLOPS. In Cadence encounter, we get a full down to flip-flop view; but here as in attached image, clk/reset is not shown connected to anything, and it always use thick bus lines to hide group of signals without allowing you to expand it. To show how arrogant Quartus is I put both RTL and tech mapping view screenshot here.

https://alteraforum.com/forum/attachment.php?attachmentid=15064&stc=1

Could you advise me how to

  1. Show full connection, i.e., give me clk and reset’s connection to registers.

  2. To break those obscuring thick buses, give each single wire connection

  3. The primitive shown in the tech-map view, is akin to the final LUT in CPLD, which is understandable since it eases further fitting. Does Quartus allow changing the primitive to most-basic FLIP-FLOPS?

greg

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    You code does not describe a register, hence why there are no registers in the RTL views, just inferred latches. You have it as if using both reset and clock as clocks. You need to change the code to: 

    
module test_grammar (count, clk, reset);
output  count;
input clk, reset;
reg  count;
initial
begin
count=0;
end
always @ (negedge clk or posedge reset) begin
  if reset begin
    count <= 0;
  end
  else begin
    count<=count+1;
  end
end
endmodule
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    The problem would be clear if you don't ignore the synthesis warnings given by Quartus:

    --- Quote Start ---

    Critical Warning (10237): Verilog HDL warning at test_grammar.v(14): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Thansk.

    Is there a way to have Quartus always expand the thick bus lines to thin individual lines, like by default showing "connectivity details"?
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    What exactly do you want to see? It always shows the bus names.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    In most CAD tools, say Cadence, they allow representing multiple related wires bus, which is convenient; but they also allow showing individual wires without bus, and it is a matter of choice in drawing the design. For Quartus, I would like to know if there is setting/preference or command line option to make it by default disable individual wires instead of thick bus.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    --- Quote Start ---

    In most CAD tools, say Cadence, they allow representing multiple related wires bus, which is convenient; but they also allow showing individual wires without bus, and it is a matter of choice in drawing the design. For Quartus, I would like to know if there is setting/preference or command line option to make it by default disable individual wires instead of thick bus.

    --- Quote End ---

    The Netlist viewers are not CAD tools - you cannot change the design on these viewers.

    Why not explain why you want to see these things, and maybe we can help/explain a better way to do it?