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Honored Contributor
Honored ContributorQuartus show only dumber's incomplete view
Hi, It feels like being treated as a dumb by Quartus. For example, we have a very simple add one counter, `timescale 1ns / 1ns module test_grammar (count, clk, reset); output [1:0] ...
Altera_ForumHonored Contributor
Honored ContributorThe problem would be clear if you don't ignore the synthesis warnings given by Quartus:
--- Quote Start --- Critical Warning (10237): Verilog HDL warning at test_grammar.v(14): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead --- Quote End ---
