Quartus reporting unconstrained inputs and outputs on constrained paths

Hi I have implemented a set of timing constraints on my Arria 10 design and I'm confused about two things. [Running Quartus Pro 22.1]

1. Quartus is reporting one of my input clocks (it is a differential clock, I'm not sure if this matters) as an unconstrained input port.

I have set the clock constraint as:
create_clock -name {chs_clk_rx} -period 150.000MHz [get_ports {chs_clk_rx}];

*I know the -period 150.000MHz is odd but the timing analyzer accepts it. I have additional input clock pins that are also differential signals that I set, for example:

create_clock -name {lvds_rx_1} -period 150.000MHz [get_ports {s1_lvds_in[1]}];

This signal does not show up as an unconstrained input port. Is there any reason why one might show up differently than the other?

2. I have a whole bunch of differential output signals where I have assigned an output delay constraint (or assigned a generated clock to output clocks) and the negative pin of the differential pair is showing up as unconstrained.

My understanding with differential pair timing constraints is we only constrain the positive edge so that the timing analyzer doesn't try to run two separate paths. Is this incorrect?

An example of the constraint in question:
create_generated_clock -name lvds_tx_1 -source [get_pins {i_pll_lvds|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}] -master_clock [get_clocks {i_pll_lvds|iopll_0|outclk1}] -divide_by 1 -multiply_by 1 [get_ports {s1_lvds_out[1]}]

The positive pin is showing as constrained but the s1_lvds_out[1](n) is showing unconstrained.

Some advice would be greatly appreciated!