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TMayd's avatar
TMayd
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Quartus reporting unconstrained inputs and outputs on constrained paths

Hi I have implemented a set of timing constraints on my Arria 10 design and I'm confused about two things. [Running Quartus Pro 22.1] 1. Quartus is reporting one of my input clocks (it is a differ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


In this case you are using the dedicated LVDS block inside the FPGA, so you only need to assign constraint on the positive pin. In this case I would also suggest you to do the same for the assignments you have added in your .qsf/.tcl file; only set them for the positive pin, it would automatically be applied on the negative pin.


If you are using normal IO to form LVDS, only then you need to assign constraints for both pins.


Regards,

Nurina