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TMayd's avatar
TMayd
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Quartus reporting unconstrained inputs and outputs on constrained paths

Hi I have implemented a set of timing constraints on my Arria 10 design and I'm confused about two things. [Running Quartus Pro 22.1] 1. Quartus is reporting one of my input clocks (it is a differ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


I have consulted LVDS expert.

Below is outcome from our discussion:

The negative pin is only contra from positive pin, the timing is also exactly the same, only inverted in terms of voltage. Timing wise, this is the same timing.

So, if you are using LVDS differential pins for LVDS, then you only need to constraint the positive pin.

If you are using normal IO pin to perform LVDS, then you need to constraint both pins.


I hope this clears things up, please let me know if you have any further questions.


Regards,

Nurina