Quartus Problems

You didn't provide much about your design or method to work with looking for your problem. You already suspect you need to do timing constraints. That is generally true. The book HDL chip design by Douglas Smith is very practical and gives a great overview of how to do design, such as what matters and how do it. Do you use synchronous design techniques? Do you use a global asynchronous (i.e. power up) reset?

I am using a Logicport 32 channel PC based logic analyzer hooked up to divider outputs from the FPGA. The fpga always programs properly. When I have the "erratic behavior" the outputs of the dividers as seen on the logic analyzer just appear dead - no division, no output at all. This must have to do with my own ignorance of using Quartus because if others had this problem I think this forum would be one big hate Quartus party! I just don't understand why when I seem to have something working properly just adding another piece of unrelated logic can stop the whole system in its tracks. I am not trained in digital logic but have studied Verilog on my own and built my share of 4000 and 7400 series of logic circuits. By the way, this is not just a problem with my own logic circuits. Some of the Altera DE2 examples from Terasic have similar problems. Just changing one simple thing can affect unrelated modules and give unexpected results. Come on, tell me if I am being stupid or admit that this has happened to some of you also! Thanks again.

There is no short answer until you have verified the basics. After ensuring your part is running with the basic assumptions met, then yes you need to make your design synchronous and apply timing constraints.