Quartus Prime20.1 can't compile systemverilog syntax

Hi,

Yes, recursive functions can be used in the compiler tools. But just a heads up, if you use the recursive functions like the way below (example):

module factorial_fail (input [7:0] ip, output reg [7:0] we);

function automatic [7:0] factorial;

input [7:0] i_Num;

begin

if (i_Num == 1)

factorial = 1;

else factorial = i_Num * factorial(i_Num-1); end endfunction

always @ ip

begin we = factorial(ip); end

endmodule

You probably will get this Error(14408): Verilog HDL error at factorial_fail.sv(3): stack overflow on recursion via factorial, limit of 900 has exceeded

So in order to pass the synthesis for recursive functions, have to implement the module with input values to the recursive function as follows:

module factorial (input [7:0] ip, output reg [7:0] we);

function [7:0] factorial1 (input [7:0] i_Num);

if (i_Num == 1)

factorial1 = 1;

else factorial1 = i_Num * factorial1(i_Num-1); endfunction

assign we = factorial1(8'd4);

endmodule

Thanks,

Best Regards,

Sheng