Quartus Prime20.1 can't compile systemverilog syntax

Here is my code:

class iTreeNode;
NodeType ntype;
class ExNode;
int size;

function new();
size = 0; // 设置默认值
endfunction

endclass
class InNode;
iTreeNode left;
iTreeNode right;
int splitAtt;
int splitValue;
function new();
splitAtt = 0; // 设置默认值
splitValue = 0; // 设置默认值
endfunction
endclass
ExNode exNode;
InNode inNode;
function new();
// 初始化联合体成员
exNode = new;
inNode = new;
ntype = EXTERNAL_NODE; // 设置默认值
endfunction
endclass

I use classes because I need nested definition. These codes can be compiled and run successfully in Modelsim. I guess maybe the Quartus dosent support the systemverilog in some aspects.