Forum Discussion
xxerexxaa
New Contributor
New ContributorQuartus Prime20.1 can't compile systemverilog syntax
我在使用modsim编译成功并且成功仿真以后想使用quartus烧录至FPGA上发现许多类似于class 和数学函数的使用在quartus里无法编译。 我已经修改了quartus prime 20.1 的编译器为SystemVerilog但是还是无法编译class。请问有人遇到类似的情况吗？ 据我所知可能是软件本身的问题，但是我的导师希望我最好还是使用quartus，所以请问有什么比较好的不...
sstrell
Super Contributor
Super ContributorIt might help to post the code and the exact errors you are getting.
xxerexxaaHere is my code:
class iTreeNode;
NodeType ntype;
class ExNode;
int size;
function new();
size = 0; // 设置默认值
endfunction
endclass
class InNode;
iTreeNode left;
iTreeNode right;
int splitAtt;
int splitValue;
function new();
splitAtt = 0; // 设置默认值
splitValue = 0; // 设置默认值
endfunction
endclass
ExNode exNode;
InNode inNode;
function new();
// 初始化联合体成员
exNode = new;
inNode = new;
ntype = EXTERNAL_NODE; // 设置默认值
endfunction
endclassI use classes because I need nested definition. These codes can be compiled and run successfully in Modelsim. I guess maybe the Quartus dosent support the systemverilog in some aspects.
