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ELIT1's avatar
ELIT1
Icon for New Contributor rankNew Contributor
2 years ago

Quartus Prime Pro 24.1 RAM Inference problems

When trying to infer Block-RAM from the attached System Verilog code the following problems occurred: 1 - when used 'rd_outcken' input (RDOUTCKEN_USED = "YES") - out registers not packed to memory ...
Hdl
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Not sure if you have further question on this? If no, we shall close this forum thread.


Thanks,

Best regards,

Kenny Tan


ELIT1's avatar
ELIT1
Icon for New Contributor rankNew Contributor
2 years ago

Hi,

I will continue to use RAM, created by Quartus Prime Pro 24.1 IP PARAMETERS EDITOR.

Please, close this thread.

Thanks,

ELIT1