Forum Discussion

ELIT1's avatar
ELIT1
Icon for New Contributor rankNew Contributor
1 year ago

Quartus Prime Pro 24.1 RAM Inference problems

When trying to infer Block-RAM from the attached System Verilog code the following problems occurred: 1 - when used 'rd_outcken' input (RDOUTCKEN_USED = "YES") - out registers not packed to memory ...
Hdl
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi, I manage to download your design to take a look.


One way to understand what are the RAM supported setting is by pulling out the IP from the IP catalog. Set whatever setting that you want and generate out the IP. From there, you can copy out the generated output content of the IP to your design to see what is actually supported.


I attached a screenshot for you to refer. Thanks


  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Screenshot attached