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New Contributor

1 year ago

Quartus Prime Pro 24.1 RAM Inference problems

When trying to infer Block-RAM from the attached System Verilog code the following problems occurred: 1 - when used 'rd_outcken' input (RDOUTCKEN_USED = "YES") - out registers not packed to memory ...

sdpram.7z1 KB

Hdl

sstrell

Super Contributor

1 year ago

There is no "rd_outcken" signal in the memory blocks so that has to get implemented in a separate register, as you note.

Similar issue on the write side: there is no "wr_cken" signal for the memory blocks, so it has to add an AND gate up front.

https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/simple-dual-port-dual-clock-synchronous-ram.html

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Quartus Prime Pro 24.1 RAM Inference problems

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