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ELIT1
New Contributor
New ContributorQuartus Prime Pro 24.1 RAM Inference problems
When trying to infer Block-RAM from the attached System Verilog code the following problems occurred: 1 - when used 'rd_outcken' input (RDOUTCKEN_USED = "YES") - out registers not packed to memory ...
sstrell
Super Contributor
Super ContributorThere is no "rd_outcken" signal in the memory blocks so that has to get implemented in a separate register, as you note.
Similar issue on the write side: there is no "wr_cken" signal for the memory blocks, so it has to add an AND gate up front.
