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Altera_Forum's avatar
Altera_Forum
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9 years ago

Quartus Prime Lite SignalTap II Logic Analyzer usable with MAX V?

Hi In the spec sheet on the MAX V CPLD is says "You can debug your MAX V designs using In-System Sources and Probes Editor in the Quartus II software. This feature allows you to easily control any...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Some USB blaster clones don't support everything that signaltap needs. This might be your problem.

Knug's avatar
Knug
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5 years ago

Is this the case? Signal Tap only supported for FPGAs instead of CPLDs (eg MAX V).

Seen in a Video that ELA only works with FPGA designs and not CPLDs because of the availability of memory in Intel FPGA devices. It stated need available LBs to implement the Logic Analyzer itself + Memory blocks to store/capture data samples.

Was looking today to add signal Tap to check my design but looks like this is not feasible for MAX V device. Please confirm