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KenCiszewski's avatar
KenCiszewski
Icon for New Contributor rankNew Contributor
1 year ago

Quartus Prime issue

I'm learning Quartus Lite using the MAX II EPM240 CPLD. I was able to compile successfully based on https://eecs.blog/max-ii-cpld-basic-getting-started-tutorial/, a simple counter/divider design...
Hdl
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago
Before assigning in- and outputs, the design schematic must be connected completely. Looks like counter is an empty box with no HDL code associated it, thus it doesn't show in- and outputs in pin planner.