Forum Discussion
Altera_Forum
Honored Contributor
16 years agoAssuming you're set for VHDL 1993 compilation (the default) you dont need a component declaration at all. Use this method instead:
pll1_inst : entity work.pll1 PORT MAP (
areset => areset_sig,
inclk0 => inclk0_sig,
c0 => c0_sig,
locked => locked_sig
); This method looks for the entity in the source file instead (make sure the pll1 source file is included in the project).