Quartus PLL - How to connect to existing VHDL

No problem. If you insert the MegaWizard generated instantiation template, you have this code in your architecture body.

pll1_inst : pll1 PORT MAP (
  areset	 => areset_sig,
  inclk0	 => inclk0_sig,
  c0	 => c0_sig,
  locked	 => locked_sig
);

areset and locked are optional signals enabled by default, you don't need them most likely. inclk0_sig should be connected to your clock (you can place the input port signal on the right side of the assignment directly) and c0_sig is your PLL generated clock. Of course, the signal must be defined in the architecture.