Trying to configure a basic PCIe interface on the Agilex F014 EVM, and the P-Tile IP configuration crashes if I disable either the read-data-mover or write-data-mover functions under the Avalon-MM Settings tab. Re-enabling the data-mover button leaves the configurator in a persistently confused state. Something bad is happening during core elaboration. I don't have a streaming-data application, so the ST core isn't useful. I don't have any DMA support in my system (hence the desire to disable the data-movers.) This issue exists in Quartus 22.3 and 22.4. We have a system with PCIe-to-Avalon-MM running on a Cyclone 10GX and it works fine. We want to have comparable functionality on our Agilex-based boards, but the P-Tile core appears to be broken. Screen shot and error log are attached.

Hi,May I know why you disable those features ? is there any unavoided specific reason doing that ?Regards,Wei Chuan

Hi, I wish to follow up with you about this case.Do you have any further questions on this matter ? Regards,Wincent_Intel

I am working with multiple platforms that have PCIe interconnect as the only available control-plane interaction. These are deployed systems, so a design constraint is to use the existing memory-mapped PCIe control paradigm. The host controller sets operating parameters via memory-mapped port writes, reads machine status via port reads, responds to interrupts on the various cards, and blinks LEDs ... you know, normal hardware-system tasks. The target cards are big state machines with no local processor. The system does not operate with DMA-anything. We are not transferring blocks of data in a packet/protocol structure. We disabled the DMA data movers because they have zero place in our system architecture. We just need memory-mapped control ports, and legacy interrupts to trigger event responses. We have these operational with Stratix 10 and Cyclone 10 FPGAs, and they work fine. We are migrating to an Agilex-based design, and that's where we bashed into the P-Tile support issue. Functionally, the P-Tile should be able to handle a memory-mapped Avalon interface. We found this bit in the documentation disturbing - Note: Do not use the P-tile Avalon® Memory-mapped IP for PCI Express* for new designs. This IP will not be available in future releases of Intel® Quartus® Prime. For new designs, use the Multi-Channel DMA IP. (ref: https://www.intel.com/content/www/us/en/docs/programmable/683853/21-1-4-0-0/design-example-overview.html ) Not sure why Intel/Altera would think that there's no place for direct-mapped port-I/O construct in a hardware-based platform ...

Hi, I did a double-check on that, what wroten in the user is correct. If you believe your business case justifies that Intel should invest in providing P-tile Avalon® Memory-mapped IP for PCI Express* My suggestion will be please work directly with your cognizant Sales/FAE to submit this feature request. Regards, Wincent_Intel

Thank you for verifying. Not sure how we are going to proceed. Intel's recommendation to use the Multi-Channel DMA IP for memory-mapped applications doesn't appear to be a workable solution - legacy MSI interrupts aren't supported, and MSI-X interrupts appear to be broken as far back as 22.1 ... seems you're SOL if you need interrupt support across the PCIe connection. The following summarizes known issues in the current IP release [v22.1]: Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the User MSI-X feature in the Multi Channel DMA Intel FPGA IP for PCI Express is not functional. https://www.intel.com/content/www/us/en/docs/programmable/683821/22-1/known-issues.html Explains why the MSI-X radio button and subtended selections in Quartus are not-selectable.

Quartus P-Tile PCIe IP config crashes | Altera Community

27 Replies

jmcguire3
Occasional Contributor
3 years ago
Allow me to clarify my upthread claim that Intel isn't using the PCIe Avalon-MM IP core in their own demo design. If you open the included demo design, you'll see that there's a "generic component" implemented, that happens to have its name assigned to that of the busted IP Core. Maybe Intel was hoping nobody would notice that they're not using their own IP ...

The generic core has a Big List o' Parameters ... nominally 2000 of them ... unrolled as a flat-file list. The API we are looking for is the one that identifies and describes every one of these parameters such that we, the community, may community-support ourselves.
Wincent_Altera
Regular Contributor
3 years ago
Hi,

Please accept my apology for late reply.
I take a deep look back on your issue , i found that although the AVMM is not longer support in Quartus v22.3 and 22.4
BUT... it did support in older version. Alternative suggestion to you is to revert back into Quartus v22.1.

Hope this suggestion is able to help you move on.

Regards,
Wincent_Intel
Wincent_Altera
Regular Contributor
2 years ago
Hi,

Do you able to try in Quartus v22.1 ?
Let me know if there is anything I can help you more.

Regards,
Wei Chuan
Wincent_Altera
Regular Contributor
2 years ago
Hi,

I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket

Regards,
Wincent_Intel
Wincent_Altera
Regular Contributor
2 years ago
Hi,

I believe I had answered your question.
As there is no reply from you, I shall proceed to close this case on my place.
Hence, This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
If you feel your support experience was less than a 9 or 10,
please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,
Wincent_Intel
jmcguire3
Occasional Contributor
2 years ago
Reverting back to v22.1 won't help me. My development requires v22.3 or newer.

If, while community-supporting myself, I stumble into any solutions, I will post them here. Maybe. Might take a shot at seeing if I can implement the MCDMA PCIe core with the AVMM support, but that's going to take a lot of additional effort to convert to the MSI/MSI-X interrupt structure.

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Quartus P-Tile PCIe IP config crashes

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