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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus not synthesizing my FSM right?

I made a FSM in verilog that is working in simulation. I found a strange behaviour however, when I synthesize it in Quartus 2. The state WRITE should immediately go to WRITE_DONE, which it does. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I believe I found the problem in my code. I think a latch was being inferred during synthesis.

I added 'next_state = state' before the case statement (where the next_state = IDLE is commented out) and it works now.

I thought the default state would prevent this, but I guess not. Thanks everyone.