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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus not synthesizing my FSM right?

I made a FSM in verilog that is working in simulation. I found a strange behaviour however, when I synthesize it in Quartus 2. The state WRITE should immediately go to WRITE_DONE, which it does. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Couple of things to check

1. Make sure your signaltap clock is the same as your state machine clock

2. Take a look at Synthesis report -> State Machines section. Check if all your states are synthesized correctly and nothing got optimized.