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Altera_Forum's avatar
Altera_Forum
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15 years ago

Quartus issuing error message for Memory Interface design

Hi, I have two interfaces PCI and DDR2 memory controllers targeting same FPGA of Cylcone III family. When I ran that case I am getting the following errors. Can some one explain what it exactl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

There´s certainly a PLL inside the DDR2 controller. So the clk input of the controller leads to the PLL. I can´t check on a short notice it for you, because the controller doesn´t show up in my IP list. Probably there´s something misconfigured over here. Maybe someone else can help you for this.You are using SOPC builder I suppose?

Good luck, Ton