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Altera_Forum's avatar
Altera_Forum
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15 years ago

Quartus issuing error message for Memory Interface design

Hi, I have two interfaces PCI and DDR2 memory controllers targeting same FPGA of Cylcone III family. When I ran that case I am getting the following errors. Can some one explain what it exactl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Check where the input clock of your PLL is coming from. The clock source you use is not allowed and therefore disconnected.

Regards, Ton