Altera_ForumHonored Contributor14 years agoQuartus II time limited .sof file Hi, when I try to program my FPGA...it appears a advice window about a limited time .sof file generation...as shown in attached image. I'd like to know how I have to behave... RegardsShow Morequartus error.jpg35 KB
Altera_ForumHonored Contributor8 years agoYes you can see the EMAC signals in signaltap, even if you don't have a license.
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: