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Altera_Forum
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12 years ago

Quartus-II synthesis/compile errors for Arria V device

I have been using Altera devices (Stratix, Cyclone and others) for more than 20 years. Recently our company decide to use the new Altera Arria V device. Our project has a lot math calculations of sig...
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Altera_Forum
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12 years ago

Hi Shuo

This sounds like a bug with Quartus. I have found bugs with various tools sets in the past with Both Xilinx and Altera's tools.

It sounds like you have already isolated the issue in the gate level netlist to a specific path. I would submit a test case to Altera describing the issue and send them both the original RTL and the gatelevel netlist. The more you can isolate the issue the better. (IE if you can make a simple design that still exhibits the error it's easier for them to pinpoint the problem).

Of course, they'll also want to know your tool version, and will want you to be on the latest version before continuing. So if you are not already there, I would download the latest from software.altera.com and try the compile again, to see if it's been resolved.

Regards

Pete