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Altera_Forum's avatar
Altera_Forum
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14 years ago

quartus II synthesis issue

I am facing a problem in using quartus II 11.0 . Is there any option to disable I/O insertion while generating the netlist file after "Analysis & Synthesis" is run i.e. after Synthesis stage...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

thanks for the reply,

i haven't used the virtual pins before. so please can u explain how will this help?? one more issue is that quartus uses the quartus_map command to do synthesis followed by the mapping so if i want to restrict it only to do synthesis then what is the way?? actually i need the netlist generated after synthesis but before mapping.

thank you

Siddharthm