Quartus II pll module synthesis error

Recently, When my design contains PLL module either introduced by ddr2 controller or manually added, i will encounter error messenges like following:

Error (10130): Verilog HDL error at ddr2_display_phy_alt_mem_phy_pll.v(144): parameter "bandwidth_type" is not a formal parameter of instantiated module

Error (10130): Verilog HDL error at ddr2_display_phy_alt_mem_phy_pll.v(145): parameter "clk0_divide_by" is not a formal parameter of instantiated module

and more....

Does any one have experience of solving this kind of issue

and any idea is welcomed.