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Altera_Forum's avatar
Altera_Forum
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15 years ago

Quartus II pll module synthesis error

Recently, When my design contains PLL module either introduced by ddr2 controller or manually added, i will encounter error messenges like following:

Error (10130): Verilog HDL error at ddr2_display_phy_alt_mem_phy_pll.v(144): parameter "bandwidth_type" is not a formal parameter of instantiated module

Error (10130): Verilog HDL error at ddr2_display_phy_alt_mem_phy_pll.v(145): parameter "clk0_divide_by" is not a formal parameter of instantiated module

and more....

Does any one have experience of solving this kind of issue

and any idea is welcomed.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You have given very vague description but one possibility is that PLL instant is meant for another device family than the device selected in your project.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I have the same question!

    I feel no the another family

    but have another way to solve this question is that you built the PLL in QII don't sopcbuilt

    in sopcbuilt I can't