Quartus II newbie questions

Jake,

I really appreciate the time you are taking to answer here.

But it seems that this discussion is not going anywhere.

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By inconsistencies I believe you mean "doesn't behave like ISE"

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I don't think I ever said or inferred that Quartus should behave like ISE. I actually did not mentioned Xilinx or ISE before you did.

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What version of Quartus II are you using?

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I mentioned in the initial post:

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I recently installed the latest Quartus II 8.0 SP1

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When I say inconsistencies I really mean inconsistencies with Quartus itself:

1. Instantiation template for Verilog but not for VHDL. Does it have to be ISE to treat both languages equally?

2. I thought "Analyze Current File" really means analyzing only the current file (and the modules instantiated in it). I was looking for clarification. What's wrong with this? Does it have to be ISE to do what it says?

3. Is it ISE'ish to be able to generate a test bench template for any module in a project?

Look, I understand you are a very experienced user, but not everyone is like you. Different people prefer different ways of doing the same thing (more or less productive).

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If there is something I can do to help reduce your learning curve, let me know.

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The best way to help is to discuss about what was asked and provide a solution or work around if possible.

Assuming things is usually not productive.

Thank you!

BR