Quartus II newbie questions

1 - I believe if you were to look at my code you would find it to be anything but simple. I personally can type a port list by hand faster than using the ISE generator so I don't have much use for it.

2 -

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General comments.

I thought this tool would be a friendly one. But I find important commands or options deeply hidden under misleading menus and hard to use.

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I apologize, by this statement I thought you were referring to the the intricacies of Quartus' options which is why I referred you to the documentation.

3 - By inconsistencies I believe you mean "doesn't behave like ISE". What version of Quartus II are you using?

a - Edit->Insert Template->VHDL->Constructs->Design Units->Entity (Is this not what your are looking for?). I realize it's not the same as the ISE module generator but does it meet your needs.

b - When I click on the "Analyze Current File" button on the left side of the text editor window (I normally use an external editor so this is new to me), It only analyzes the currently open file and no others.

c - Sorry I do all of my simulation directly in ModelSim so I can't field this one.

Look I use both Xilinx and Altera products and software. There are advantages to each. From your comments it appears you are very comfortable with ISE and that's probably what you have used for most of your career. No problem. I personally have found Altera's software to be superior to what Xilinx offers for reasons I won't mention here. I still use both and they both still work. Quartus II is not ISE.

I have tried to develop my design flow and methods so that I can easily transition between multiple design environments without being too dependent on each environment's unique behaviors.

Even if you remain a hard-core Xilinx user, you are going to have to adapt your flow. ISE will be replaced over the next few years with PlanAhead which at this point is substantially different from ISE. PlanAhead incorporates features that have been found in Quartus II for several years now so this is a good step for Xilinx.

I apologize for offending you. If there is something I can do to help reduce your learning curve, let me know.

Jake