Honored Contributor
Honored ContributorHi jakobjones,
Well, thank you for the answer. But you see, yes you can type your ports in 2 minutes for one module, but a real design usually has more than one. And yes, ISE does this. From what I see, Quartus does this also but for Verilog only. Don't you think this is a bit inconsistent (providing a feature for Verilog but not for VHDL)? And thank you for pointing to the documentation, but the questions here were not about "options for synthesis, place and route, etc". How about the other inconsistencies I asked in my initial post? Are there answers in the documentation about them? Thank you for helping! BR
