Quartus II newbie questions

I don't understand. If I create a VHDL file, then use Edit->Insert Template. There are more options and templates under VHDL than I can even wrap my head around.

For a component declaration, all you have to do is drop in the template. Then start double clicking on the fields and replacing them with your signal names and such.

Most people don't use code generators to create their VHDL or Verilog port lists. There is really only one platform where I know this is done and that is ISE.

I mean you're likely going to spend hours inside that module writing code. An extra 2 minutes to create a port list should be insignificant.

Altera's Quartus II documentation is quite through and covers all of the options for synthesis, place and route, etc. If you haven't taken the time yet to study the documentation, you should.