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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus II is not optimizing my synthesized circuit.

Hello everybody!

I'm Eduardo, from Venezuela. I'm an EE student and I'm new to this forum :)

I have what you may call a noob's question, but I can't get Quartus II to reduce the size of the synthesized gate-logic circuit. I know that the function I'm implementing (a simple boolean function) can be reduced at gate level, but when I click on "RTL Viewer" on Tools, there is actually no simplification :/ And I have tried almost anything to achieve it, but still no success.

This is what I get on the RTL Viewer:

http://www.alteraforum.com/forum/attachment.php?attachmentid=11172&stc=1

What I should get (took from textbook)

http://www.alteraforum.com/forum/attachment.php?attachmentid=11171&stc=1

I performed a wave vectors simulation of both the code I used and the code they use in the textbook and they match, so the code is not the problem.

I really hope you can help me and later I can help you too as long as I keep learning :)

Thanks in advance!

=)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    The RTL Viewer will show you basically what you coded. It's the map view that will show you the reduced circuit.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for answering, Tricky, but all I can see is a "black box" with input and output pins on the Technology Map Viewer :/

    PD: I accidentally deleted the original post when trying to remove an unused thumbnail xD sorry.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    You won't get the "optimized" version anyway because an FPGA doesn't use gates internally, it uses look-up-tables. Your logic can be synthesized in a single LUT cell and that is probably what the technology map viewer is showing you.