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Altera_Forum's avatar
Altera_Forum
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11 years ago

Quartus II is not optimizing my synthesized circuit.

Hello everybody! I'm Eduardo, from Venezuela. I'm an EE student and I'm new to this forum :) I have what you may call a noob's question, but I can't get Quartus II to reduce the size of the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You won't get the "optimized" version anyway because an FPGA doesn't use gates internally, it uses look-up-tables. Your logic can be synthesized in a single LUT cell and that is probably what the technology map viewer is showing you.