Quartus II Internal Error

Unfortunately I have zero experience with system verilog.... (Need to get some training on it as soon as I can find a week to go to a class..)

But it could be one of the following: Nested interfaces aren't supported yet in synthesis.. (it should catch it earlier in the compile stage and tell you though).

Or your uses of () is confusing it..

Try changing

interface data_reg_read_intfc;

bit [15:0] data;

bit [3:0] addr;

modport syn_test(input data, output addr);

endinterface

interface regfile_EXU_intfc (input bit clk, rst);

data_reg_read_intfc drr_intfcs ();

// bit asd_en;

// modport syn_test(input asd_en);

endinterface

to

interface data_reg_read_intfc;

bit [15:0] data;

bit [3:0] addr;

modport syn_test(input data, output addr);

endinterface

interface regfile_EXU_intfc;

bit clk, rst;

data_reg_read_intfc drr_intfcs ();

// bit asd_en;

// modport syn_test(input asd_en);

endinterface

It's a minor difference, but may be the source of this issue.. I don't know if what you did was valid or not..