Forum Discussion
Altera_Forum
Honored Contributor
17 years agoAlso a range in variable definition doesn't help here. I wonder, if the variable definition is used at all when evaluating the loop range. Personally, I always use FOR LOOPS in VHDL iterations, they have a clearly defined range and give less room for misunderstandings.
By the way, most infinite loops in accidental VHDL code I've seen have been due to misunderstanding the VHDL iteration concept as means to achieve a C-like sequential program flow.