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I always have one folder or folders (containing a collection of previously used and debugged modules) containing the code and as many projects for variants or for debugging modules as I need. If designed carefully a lot of VHDL can be re-usable. Don't know if this is standard or good practice as I am self taught.
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This is much like what I do.
I have one folder that contains my source code and simulation files, usually called ./project/src/
I have folders underneath .src/ that control the revisions of my codeset (e.g. src/v0_10, src/c0_20, src/1_00 with 0_ numbers being pre-release and 1_ styled number being post release)
I have another folder that contains the build files for whatever fpga technology I am using, usually called ./project/par. That folder also contains individual folders that track the version numbers in the /src/ folders.
Both Altera and others have ways to make revisions, which Brad just wrote about and those are fine, too. I do not use them only because I have my own system independent of the big A and the big X.
BR
Honored Contributor
