Quartus II Fitter advice

Well, interesting theory, but not my experience of using Quartus over multiple designs over the last 12 years.

My designs are always pushing fmax to the limit on the device, and I would say that I almost never get the timing to close with the frequencies I'm looking for. Overconstraining by typically 5% - 10% frequently allows me to close timing (but not get a clean report).

Typically my designs have multiple clock domains and high logic utilization. And I'm talking about designs that can take 12 hours to fit on a dual penryn 1300MHz FSB machine with 32G of RAM.

I've made this a subject of many reports to local FAEs and even provided testcases to Altera of designs that won't close timing until it's overconstrained and I've never had anything useful back from them.