Hi,
This is very common problem when approaching the end of a project and appears as migratory warnings.
There are some options:
- Try design doctor from tools menu (I have tried it many times but is not efficient).
- your idea of code redesign is best. Try move as much as you can to a lower frequency clock if that is possible. Create this clock if feasible.
move as much as you can of logic to dedicated blocks(DSP or memory).
- look for any multicycle assignments. This could be very useful.
- The use of seed is good but has to be done at the very final end.
The best way is to run DSE(design Space Explorer) from tools menu and let it scan a range of seeds overnight or weekends. Remember seeds can lead
to 10% difference
Kaz