Quartus II and the funny synthesis attributes

That's funny, I had the exact problem two days ago. In a design I have I'm using 5 instances of the exact same entity. In one of them a shift function is synthesized as a altshift_taps in an M9K while the other 4 only use logic. The M9K implementation doesn't pass timing requirements while the others do...

I started using the assignment editor to fix the problem, but I don't like it because I'm sure one day the VHDL code will be reused in another project and we'll forget to put the assignment back. I could leave a comment in the code, but who reads comments... :D

So I used another solution instead, which is to give instructions to the synthesizer through VHDL attributes. Like you I had so luck with the ramstyle attribute, but this one works very well:

	--! Altera synthesizer instuctions attribute
attribute altera_attribute : string;
	--! Instruct synthesizer not to use altshift_taps for shift registers in this entity
attribute altera_attribute of RTL: architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";

Please note that you must apply the attribute to the architecture, not the entity.